In many data communication configurations, no separate clock signal is communicated between a transmitter of a data stream and a receiver of the data stream. This requires recovering the clock from the data stream at the receiving end in order to then recover the data. This problem often arises when transferring digital data across one or more clock timing domains. It is not unusual to transmit digital data between clock timing domains having nearly the same underlying frequency clock, but different or varying phases with respect to each other.
The receiving end can derive a sampling signal from the data stream, and then use the sampling signal to sample the received data at sample times that produce optimal data recovery. In this way, data recovery errors can be minimized. Precision timing control techniques are desirable to achieve and maintain optimal sampling times, especially when the received data stream has high data rates, such as multi-gigabit-per-second data rates. Such timing control includes control of the phase and frequency of a sampling signal used to sample the received data signal.
As received data rates increase into the multi-gigabit-per-second range, the difficulty to effectively control the sampling phase in the receiver correspondingly increases. This problem is further aggravated at multi-gigabit frequencies since the data eye width (the period of time during which the received data is valid for sampling) decreases with increasing frequency.
Phase interpolators are often used to precisely position the sampling phase at the center of the received data eye. To maximize the setup and hold time margin, the sampling clock should be positioned with high precision and jitter minimized. Additionally, since chip performance is becoming limited by power delivery, reducing power consumption of a phase interpolator helps achieve high performance sampling.